The process of RE-layout design has caused companies to spend small fortunes in limited human resources. The turn around time for a RE-layout is equal to several man years.
FIG. 1 shows a typical redesign process for a chip layout for new design rules. The prior art redesign process takes the chip layout 10 and breaks down the layers into symbols representing elements such as transistors 12. The original chip layout is used to draw a symbolic form which is hierarchical. Based on the new design rules the symbols are moved to optimize chip layout according to the new design rules 14. The process of drawing the original chip layout in symbolic form 12, laying out a new symbolic form 14, and creating a new chip layout 16 is extremely labor intensive.
What is needed is a way to reduce the labor-intensive conversion of chip layout to symbolic form, creating a new symbolic representation based on the new design rules, and converting the new symbolic representation to a chip layout for fabrication.